This invention relates generally to logic gate circuits and more particularly to logic gate circuits which include field effect transistors and which are adapted for large scale integration (VLSI) applications.
As is known in the art, metal-semiconductor-field effect transistor (MESFET) logic gate circuits have been discussed in the literature. These circuits may generally be separated into two classes of logic gate circuit designs: direct coupled logic circuits based on enhancement mode MESFET devices; and, buffered, level-shifted logic circuits basen on depletion mode MESFET devices. Generally all depletion mede MESFET logic gate circuit designs require voltage level shifting, typically requiring a negative V.sub.SS voltage supply in addition to a positive V.sub.DD voltage supply. The level-shifting operation generally implies the presence of a static current for forward biasing reference junctions of the devices used in the gate circuit and a minimum supply voltage needed to overcome the built-in junction potentials. Such gate circuits therefore also require relatively large amounts of power.
Enhancement mode MESFET logic gate circuits generally include directly coupled devices obviating the need for logic shifting circuitry. One such suggested logic circuit includes a plurality of input MESFET devices wired to provide an AND circuit. Such previously proposed enhancement mode MESFET gate circuits however have relatively little noise immunity because they are limited by the low threshold voltages of the input MESFET devices and by accumulating series drops across those devices.